Field
Implementations herein are directed generally to frequency detection, and aspects may involve phase frequency detection, handling missing edges of reference and/or feedback clocks, and/or increasing gain of phase frequency detectors.
Description of Related Information
Phase locked loop (PLL) and Delay Lock Loop (DLL) circuits are widely used in clock generation for a variety of applications including microprocessors, wireless devices, serial link transceivers, and disk drive electronics, among others. FIG. 1 illustrates a block diagram of a typical charge-pump based PLL circuit design, including a Phase Frequency Detector (PFD) 108, Charge Pump (CP) 112, Loop Filter (LPF) 116, Voltage Control Oscillator (VCO) 120, and multiple Dividers 104, 128, 124. Here, a Phase Frequency Detector (PFD) 108 is an important component in a Phase locked loops (PLL) or a Delay locked loop (DLL), such as in the PLL of FIG. 1. The Phase Frequency Detector 108 compares two clock inputs and generates UP and DOWN signals to control the Charge Pump. FIG. 2 illustrates a conventional Phase Frequency Detector PFD 200 and a conceptual charge pump 206.
In operation, a Phase Frequency Detector PFD 108 responds to the phase difference between the input reference clock (ckref) and the input feedback clock (ckfb) and generates UP and DOWN signals which switch the current in the charge-pump (CP) 112. FIG. 3 illustrates an exemplary relationship between the charge pump current Icp and the phase difference ΔΘ between the reference clock and the feedback clock, including an ideal linear PFD characteristic 302 of this relationship. Further, to avoid dead-zone issue, PFDs typically have a RESET delay path to guarantee minimum pulse width. This nonzero reset delay will reduce the linear range of the PFD to be less than 4π and causes non-ideal behavior 304 for the PFD, as shown in FIG. 3, as well as non-ideal behavior 406 (missing edge) shown in FIG. 4.
The nonzero reset delay sets a limitation for the PFD operating speed. As shown in FIG. 4, due to the nonzero reset delay, the 2nd ckref rising edge arrives while the Reset signal (rstb) is still in effect. The rstb overrides the 2nd ckref rising edge and thus doesn't activate the Up signal, whereas the subsequent ckfb rising edge causes the Down signal to show up first. Consequently, the phase difference (ckref−ckfb) appears as negative instead of positive.
Such gain reversal 408 may occur periodically during PLL lock-in process with conventional Phase Frequency Detector, and thus may both slow down the PLL frequency acquisition dramatically, and sometimes cause a PLL to fail in acquiring frequency lock.
FIG. 5 illustrates a general timing diagram for other existing Phase Frequency Detectors (PFDs) with features related to detection of missing edge(s). Note that there is no reversal gain, since the 2nd ckref rising edge will trigger the 2nd Up rising edge 502, though the 2nd rise of the ckfb signal still generates the Down and the reset signals, and therefore limits the PD gain to be flat near+/−2π.